Vous êtes ici : Accueil > PRESSE > CEA-Leti Scientists Demonstrate CMOS Device Fabrication at 500°C (contenu en anglais)

Communiqué de presse | Actualité | Nouvelles technologies

CEA-Leti Scientists Demonstrate CMOS Device Fabrication at 500°C, Paving the Way to High-Performance 3D Monolithic CMOS Integration


​VLSI 2020 Paper Details First Proof of Integration of FDSOI CMOS Devices Processed at 500°C, for Further 3D Monolithic Integration

Publié le 22 juin 2020

​GRENOBLE, France – June 22, 2020 – In an FDSOI CMOS processing breakthrough, CEA-Leti scientists have pushed fabrication thermal-process boundaries down to 500°C for CMOS integration, while showing strong performance gains especially in P-type metal-oxide-semiconductor (PMOS) logic devices.

  • The 500°C threshold is important because in 3D monolithic technologies (also called 3D sequential), fabricating the upper-level transistors at higher temperatures than that can damage the metal interconnects and the silicide of the bottom-level transistors. Using CEA-Leti's CoolCubeTM low-temperature process for top-level devices prevents deterioration of bottom-level transistors. 


Integration of CMOS devices is now possible at 500°C on top," said CEA-Leti scientist Claire Fenouillet-Beranger. "This proof of concept gives more and more credibility to this sequential integration for applications requiring high densit



​(a) HR STEM image of pMOS device (b) Phase image of pMOs device acquired by off-axis electron holography. (c) Profile showing the step in potential across the region indicared in (a) resulting from the active dopants.(c) Claire FENOUILLET-BERANGER 
3D sequential integration becomes more and more attractive for More Moore and More than Moore applications," the paper reports. "One of the main advantages of this 3D technology vs. a die-to-die one, for instance, is the major gain of density brought by the nanometer-scale lithographic alignment between the two levels. However, one of the most important challenges is to implement at low temperature high performance CMOS devices for the upper level, after fabrication of the bottom level devices.

           

​Artefact 3D TEM effect(c) Claire FENOUILLET-BERANGER 


"The maximum temperature regarding bottom device's silicide integrity and inter-tier interconnections preserved reliability should not exceed 500°C for a couple of hours," the paper reported. "Several low-temperature devices have been published in literature, but up to our knowledge, this is the first proof of integration of CMOS devices processed at a temperature of 500°C, fully compatible with advanced FDSOI platform technologies."

  • In addition, the CEA-Leti team demonstrated for the first time ring oscillators and SRAM bitcells processed at 500°C, further paving the way for high-performance 3D monolithic CMOS integration, intended for advanced logic, RF, in-memory computing, AI, imaging and display applications.



Haut de page