Starting date : Jan. 2017 > Dec. 2020 Lifetime: 48 months
Program in support : H2020-ICT-25-2015
Status project : complete
CEA-Leti's contact :
Joris Lacord
Yves Quéré
Project Coordinator: CEA-Leti (FR)
Partners: - German Aerospace Center, (DE)
- Ibeo Automotive Systems, (DE)
- IT21, (DE)
- Objective Software, (DE)
- Robert Bosch, (DE)
- Zigpos, (DE)
- BeSpoon, (FR)
- CEA-Leti, ( FR)
- Eurecom, (FR)
- FBConsulting, (LU)
- PaulsConsultancy, (NL)
- Tass International, (NL)
- Chalmers University of Technology Gothenburg, (SE)
Publications:
Investment: € 4.5 m.
EC Contribution: € 3.6 m.
| Stakes
> An A2RAM cell comprising an SOI transistor with a silicon film (approx. 25nm) thicker than CMOS applications. The film is divided into a top section used used to store information and a bottom section is used to read information. The bottom section is a buried doped layer (a bridge) that short-circuits the source and drain. > Objective: • Demonstrate that a nanowire structure can improve A2RAM performance and scaling • Demonstrate that a heterostructure between the storage region (SiGe material) and the bridge (Si material) can improve A2RAM performance.
> Process flow definition of A2RAM devices using CEA-Leti nanowire exploiting Coolcube technological developments to build the bridge:
• A2RAM structure definition by finite element simulation (TCAD): determining target film thicknesses, bridge doping and thickness, gate length and Ge quantity in the SiGe storage region • S/D implanting and annealing steps defined by TCAD • Bridge implanting and annealing steps defined by TCAD.
> Successful fabrication of nanowire-based A2RAM in a CEA-Leti clean room.
> Experimental demonstration of nanowire-based functionality of A2RAM devices:
• Demonstrating bridge presence using capacitive measurements • Demonstrating memory effect: ‘1’ and ’0’ states can be programmed and read.
> TCAD environment developed for Z2FET device simulation and shared with REMINDER partners:
• Z2FET device is a partially gated PIN diode on SOI usually dedicated to ESD applications but used here as a 1T-DRAM structure.
> In-depth knowledge of Z2FET device, especially DC hysteresis, through extensive TCAD simulations, formingthe basis of Z2FET compact model development > TCAD simulation to calibrate the Z2FET compact model
> TCAD supporting technological development involving nanowire-based A2RAM fabrication.
> Compact model development of Z2FET for project final demonstrator design: 1T-DRAM matrix using Z2FET devices. > Z2FET compact model includes: > DC behavior with hysteresis > Memory operation (write, erase and read)
> Workshop organization for 1T DRAM solutions at EuroSOI-ULIS 2019 conference in Grenoble.
OBJECTIVES
REMINDER develops an embedded DRAM solution optimized for ultra-low-power consumption and variability immunity, specifically focused on Internet of Things cutting-edge devices. The objectives of REMINDER are: - investigation (concept, design, characterization, simulation, modelling), selection and optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost;
- design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits, blocks and architectures are carefully analysed from the power-consumption point of view.
In addition, variability tolerant design techniques underpinned by variability analysis and statistical simulation technology are widely considered; - demonstration of a system on chip application using the developed memory solution and benchmarking with alternative embedded memory blocks.
The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also require the redesign of different applications, including memory cells, and therefore we also propose the evaluation of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative materials. The fulfilment of the objectives above also implies the development of: - new techniques for the electrical characterization of ultimate CMOS nanometric devices. This allows us to improve the CMOS technology by boosting device performance;
- new behavioural models, incorporating variability effects, to reach a deep understanding of nanoelectronics devices;
- advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices;
- extreme low power solutions.
The consortium supporting this project is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.
IMPACT When functional, the 1T DRAM matrix demonstrator will be a first demonstration of a 1T DRAM matrix on SOI. Close cooperation has been set up between partners Granada University, Glasgow University and Grenoble’s IMEP-LAHC laboratory, especially for TCAD simulation and electrical characterization.
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