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Starting date : January 2016
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Lifetime:48 months
Program in support
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Status project : in progress
CEA-Leti's contact :
Project Coordinator :
Helmholtz Zentrum Dresden Rossendorf (DE)
Partners: - CEA-Leti
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Fraunhofer Institute for Integrated Systems and Device Technology
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Helmholtz Zentrum Dresden Rossendorf (HZDR)
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Institute of Microelectronics Barcelona (CSIC) - Universty of Helsinki
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Consiglio Nazionale delle Richerche
Target market: n/a
Investment: € 4 mi
EC Contribution: € 4 mi
Releases“Sub-20 nm multilayer nanopillar patterning for hybrid SET/CMOS integration”, M.-L. Pourteau, A. Gharbi, P. Brianceau, J.-A. Dallery, F. Laulagnet, G. Rademaker, R. Tiron,H.-J.Engelmann, J. von Borany, K.-H.Heinig, M.Rommel, L.Baierd, Micro And Nanoengineering, (2020) Accepted paper.
"Site-controlled formation of single Si nanocrystals in a buried SiO2 matrix using ion beam mixing", X. Xu, T. Prüfer, D. Wolf, H.-J. Engelmann, L. Bischoff, R. Hübner, K.-H. Heinig, W. Möller, S. Facsko.
"Exploring Strategies to Contact 3D Nano-Pillars”, E. Amat, A. del Moral, M. Fernández-Regúlez, L. Evangelio, M. Lorenzoni, A. Garbi, G. Rademaker, M.-L. Pourteau, R. Tiron, J. Bausells, F. Perez-Murano, Nanomaterials, 10(4), pp. 716 (2020).
"Effect of the Density of Reactive Sites in P(S‐r ‐MMA) Film during Al2O3 Growth by Sequential Infiltration Synthesis", F.-E. Caligiore, D. Nazzari, E. Cianci, K. Sparnacci, M. Laus, M. Perego, G. Seguini, Advanced Materials Interfaces, 6(12), pp. 1900503 (2019).
"A Compact Model Based on Bardeen's Transfer Hamiltonian Formalism for Silicon Single Electron Transistors", F.-J. Klüpfel, IEEE Access, 7, pp. 84053 (2019).
Number of patents: n/a
| Stakes
- The aim of the IONS4SET project was to develop a framework for reliably producing SETs that operate at room temperature using a semiconductor industry process flow. The final goal was a hybrid SET/FET electrical demonstrator.
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The SET was a 10 - 12 nm diameter Gate-All Around (GAA) nanopillar with a 6 nm embeddedgate oxide (SiO2) layer. In this layer, a single 2 -3 nm diameter silicon quantum nanodot (ND) wasformed by Si+ ion implantation. During an annealing step, this silicon underwent phase separation and self-assembled into the ND. The bottom of the nanopillar was contacted electrically using the top-Si of an SOI advanced substrate.
Using the 200 mm silicon platform, CEA-Leti patterned < 30 nm diameter nanopillars, whileensuring the deposition, implantation and annealing steps for integration reasons. 20 nm diameter, 70 nm high nanopillars were created by Electron Beam Direct Write (EBDW) and etched using a standard trilayer stack. We delivered wafers to the project partners for dicing, advanced characterization and electrical integration. Energy-Filtered Transmission Electron Microscopy (EFTEM) showed that the pillars were the right size and contained a single silicon ND in the embedded oxide.
CEA-Leti also investigated Directed Self-Assembly (DSA) of Block CoPolymers (BCP) as lithography for forming nanopillars. The first method involved forming PMMA contacts using a DSA contact shrink approach based on a PS-b-PMMA BCP. Sequential infiltration synthesis (SIS) was performed: Atomic Layer Deposition (ALD) was used to replace the PMMA with alumina (Al2O3), thus forming a hard mask for pillar patterning. The second method involved a PS-b-PMMA block copolymer with an inverse matrix for forming hexagonally organised sub-20 nm PS cylinders using a trilayer stack.
OBJECTIVES
- Billions of tiny computers that can sense and communicate from anywhere are coming online, creating the Internet of Things (IoT). As the IoT continues to expand, more and more devices require batteries and plugs. Gartner (www.gartner.com) states that there will be nearly 26 billion devices connected to the IoT by 2020. Together with improved batteries, advanced computation and communication must therefore be delivered at extremely low-power consumption.
- Single Electron Transistors (SETs) are extremely low-energy dissipation devices that are complementary with CMOS: the SET is champion of low-power consumption, while CMOS advantages, such as high speed, driving, etc., compensate perfectly for the SET's intrinsic drawbacks. Hybrid SET-CMOS architectures require unrivalled integration and high performance, while manufacturability remains a roadblock for the large-scale use of such architectures. To ensure room temperature (RT) operation, single dots with diameters < 5 nm need to be fabricated and precisely positioned between source and drain with tunnel distances of a few nm. However, a reliable CMOS compatible process for co-fabricating RT-SETs and FETs is not yet available. IONS4SET's SET nanopillar paved the way for fabricating low-energy devices operating at RT based on a newly developed bottom-up self-assembly process.
- Lithography cannot deliver the 1-3 nm feature sizes required for RT operation but IONS4SET provided:
- Controlled self-assembly of single ~ 2 nm Si dots
- Self-alignment of each nanodot with source and drain at ~ 2 nm tunnel distances
- The Si nanodot fabrication process involved:
- Ion irradiation through thin (few tens of nm) Si pillars with an embedded SiO2 layer
- Thermal activation of self-assembly.
- Dot self-assembly works for narrow pillars only, hence nanopillar fabrication was crucial for IONS4SET. Finally, a power saving hybrid SET/CMOS device with a vertical gate-all-around nanowire GAA-SET was fabricated.
- The IoT demands ultra-low power electronics to improve battery life and lower carbon footprint. SETs promise to achieve those requirements because of the ultra-low current through such devices. The IONS4SET project combined fundamental physics of quantum devices and selfassembly with advanced 3D CMOS manufacturing at the 10 nm length scale. Industry interest was proven by external industry committee members GlobalFoundries, STMicroelectronics and X-Fab.
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