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ASCENT+

ASCENT+ mobilises an unprecedented network of knowledge and investment to open access to key European infrastructures and enable academic and industry researchers to address emerging challenges in Nanoelectronics and to accelerate innovation path-finding. ASCENT+ brings together 15 partners to make world-class facilities available and to foster the Nanoelectronics community. 



Publié le 17 mai 2021

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Quality of Service Provisioning and capacity Expansion through Extended-DSA for 5G

ASCENT+ mobilises an unprecedented network of knowledge and investment to open access to key European infrastructures and enable academic and industry researchers to address emerging challenges in Nanoelectronics and to accelerate innovation path-finding.ASCENT+ brings together 15 partners to make world-class facilities available and to foster the Nanoelectronics community. ASCENT+ integrates a unique research infrastructure with outstanding credentials. The partners' facilities at CEA-Leti (FR), Fraunhofer Mikroelekronik (DE), imec (BE), INL (PT/ES) and Tyndall (IE) combine research infrastructure and expertise offering an extensive portfolio to state-of-the-art processing, modelling and data sets, metrology and characterisation, and devices and test structures for Nanoelectronics 





 

Starting date : May 2015 > Apr. 2018

Lifetime: 48 months


Program in support : INFRAIA-1-2014/2015


 

Status project : complete


CEA-Leti's contact :

Olivier Faynot

 

Project Coordinator: Tyndall National Institute (IR)


Partners:  

  • Imec, (BE)
  • CEA-Leti, (FR)



​Target market: n/a

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Publications 

  • «Physics based Compact Model of Low-Frequency Noise for Gate-All-Around MOSFETs», B. Yi, G.- S. Yang, S. Barraud, L. Brevard, J.-W. Lee and J.-W. Yang; 26th Korean Conferenceon Semiconductors - Gangwon-do TB1 G6, 2019.
  • «Low Frequency Noise Variability Analysis Depending on Epi-Source/Drain in GAA (Gate-All-Around) FET», G.-S. Yang, D.-H. Kim, D.-G. Park, S.-H. Kim, J.-C. Kim, S. Barraud, L. Brevard and J.-W. Lee ; 26th Korean Conference onSemiconductors - Gangwon-do TB1 G7, 2019.
  • «Assessing the Correlation Between Location and Size of Catastrophic Breakdown Events in High-K MIM Capacitors», J. Muñoz-Gorriz, D. Blachier, G. Reimbold, F. Campabadal, J. Suñé, S. Monaghan, K. Cherkaoui, P.-K. Hurley, and E. Miranda; Trans. on Device and Materials Reliability, vol. 19, no. 2, June 2019, pp. 452-60 ; DOI: 10.1109/TDMR.2019.2917138.
  • «Effect of traps-to-gate tunnel communication on C-V characteristics of MIS capacitors», A. Mazurak, J. Jasiński, B. Majkusiak; Microelectronic Engineering, 215 (2019), pp. 111011.1-5 ; DOI: 10.1016/j.mee.2019.111011.
  • «Determination of border/bulk traps parameters based on (C-G-V) admittance measurements», A. Mazurak, J. Jasiński, B. Majkusiak; Journal of Vacuum Science & Technology B 37, 032904 (2019), pp. 032904.1-9; DOI: 10.1116/1.5060674.
  • «Functionalization of SiO2 Surfaces for Si Monolayer Doping with Minimal Carbon Contamination»,M. van Druenen, G. Collins, C. Glynn, C. O’Dwyer and J.D. Holmes; ACS Appl. Mater. Interfaces, 2018, 10 (2), pp. 2191–201; DOI:10.1021/acsami.7b16950.
  • «Williamson-Hall analysis in estimation of lattice strain in Bi1.34Fe0.66Nb1.34O6.35 prepared by the sol-gelmethod», S. Devesa, A.-P. Rooney, M.-P. Graça, D. Cooper, L.-C. Costa; submitted to Materials Science and Engineering B.
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Investment:  € 4.7 m.

EC Contribution: € 4.7 m.


Website


Stakes

  • ASCENT+ mobilises an unprecedented network of knowledge and investment to open access to key European infrastructures and enable academic and industry researchers to address emerging challenges in Nanoelectronics and to accelerate innovation path-finding.

    ASCENT+ brings together 15 partners to make world-class facilities available and to foster the Nanoelectronics community.

    ASCENT+ integrates a unique research infrastructure with outstanding credentials. The partners' facilities at CEA-Leti (FR), Fraunhofer Mikroelekronik (DE), imec (BE), INL (PT/ES) and Tyndall (IE) combine research infrastructure and expertise offering an extensive portfolio to state-of-the-art processing, modelling and data sets, metrology and characterisation, and devices and test structures for Nanoelectronics 


  • The main demands have involved (1) SOI wafers or data to develop DC, Noise, RF, ...models, (2) access to CEA-Leti models for design bench building, (3) access to advanced electrical and physical characterization tools to study university-developed new materials, devices and structures.
    The ASCENT project has enabled CEA-Leti to develop or establish new collaborations with universities in Australia, Belgium, Germany, Greece, India, Ireland, Korea, Poland, Portugal, Romania, Spain and Sweden.

  • The main demands have involved (1) SOI wafers or data to develop DC, Noise, RF, ...models, (2) access to Leti models for design bench building, (3) access to advanced electrical and physical characterization tools to study university-developed new materials, devices and structures.


  • Some examples of projects:
    Modelling of short channel effects on Nanowires FDSOI devices with University of Mittelhessen (Germany).
    Testing and modelling of 1/F noise on Nanowires FDSOI with University of Sejong (Korea).
    Study of high frequency linearity of FDSOI with Indian Institute of Technology Gandhinagar (India).
    Fabrication of a new concept of laser using PolySi with ultra small roughness with University of Cork (Ireland).
    Cryogenic test of Finfet for SPICE modelling with EOLAS Design (Ireland).
    Mobility spectrum in Nanowire SOI using magnetotransport by University of Western Australia.
    Study of ceramic nanoparticles with Transmission Electron Microscopy by University of Aveiro (Portugal).
    8 publications have been accepted to date and others are planned.


OBJECTIVES

  • The ASCENT consortium provides access to advanced nanoelectronics spanning finFET, Fully Depleted Silicon-On-Insulator (FDSOI) and flexible nanofabrication facilities. By delivering test structures and characterization data previously inaccessible to Europe’s academic modeling and characterization community, ASCENT provides access to the latest nanoelectronics technologies.

  • The objective is to accelerate the development of advanced technology computer aided design models and tools through access to electrical characterisation facilities and data, that are validated and predictive for scales extending down to just a few nanometers in critical dimensions.

  • The project will also enable the systematic characterisation of physical and processing effects arising on length scales at and below 10 nm, and to develop design capabilities for technologies at these length scales.

  • Finally, ASCENT will make all project outputs (nanoelectronic test structures, electrical characterization access and data, TCAD models, compact models) easily accessible to the nanoelectronics community through a single access portal and openly available.



IMPACT

  • Project impact has been to develop new collaborations within and outside Europe to offer universities the opportunity to access the most advanced technologies and characterization tools.

  • Several active collaborations have been directly or indirectly established:

• Direct example: fabrication of a new concept of laser using PolySi with ultra small roughness with University of Cork (Ireland).

• Indirect example: Modelling of short channel effects on Nanowires FDSOI devices with University of Mittelhessen (Germany).

  • The latter excellent relationship has opened further discussions for a collaboration on organic transistors with CEA-Liten.