Electrical characterization of vertically stacked p-FET SOI nanowires
| Auteurs | Cardoso Paz B., Cassé M., Barraud S., Reimbold G., Vinet M., Faynot O., Antonio Pavanello M. |
| Year | 2018-0056 |
| Source-Title | Solid-State Electronics |
| Affiliations | Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil, Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France |
| Abstract | This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&,R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively. © 2017 Elsevier Ltd |
| Author-Keywords | Channel orientation, Electrical characterization, Performance, SOI MOSFET, Transport, Vertically stacked nanowire |
| Index-Keywords | Characterization, MOSFET devices, Numerical methods, Si-Ge alloys, Silicon alloys, Channel orientations, Electrical characterization, Performance, SOI-MOSFETs, Transport, Nanowires |
| ISSN | 381101 |
| Lien vers article | Link |