Improvement of Sidewall Roughness of Submicron SOI Waveguides by Hydrogen Plasma and Annealing
| Auteurs | Bellegarde C., Pargon E., Sciancalepore C., Petit-Etienne C., Hugues V., Robin-Brosse D., Hartmann J.-M., Lyan P. |
| Year | 2018-0063 |
| Source-Title | IEEE Photonics Technology Letters |
| Affiliations | LTM, Centre National de la Recherche Scientifique, University Grenoble Alpes, Grenoble, France, CEA, LETI, LTM, Minatec Campus, Grenoble, France, Commissariat À l'Énergie Atomique et Aux Énergies Alternatives, LETI, Minatec Campus, University Grenoble Alpes, Grenoble, France |
| Abstract | We report the successful fabrication of low-loss submicrometric silicon-on-insulator strip waveguides for on-chip links. Postlithography treatment and postetching hydrogen annealing have been used to smoothen the waveguide sidewalls, as roughness is the major source of transmission losses. An extremely low silicon line-edge roughness of 0.75 nm is obtained with the optimized process flow. As a result, record-low optical losses of less than 0.5 dB/cm are measured at 1310 nm for strip waveguide dimensions exceeding 500 nm. They range from 1.2 to 0.8 dB/cm for 300-400-nm-wide waveguides. Those results are to our knowledge the best ever published for a 1310-nm wavelength. These results are compared to modeling based on Payne and Lacey equations. © 1989-2012 IEEE. |
| Author-Keywords | line edge roughness (LER), optical losses, photonic integrated circuits (PICs), Silicon waveguide patterning, smoothing treatments |
| Index-Keywords | Annealing, Electric losses, Etching, Optical losses, Optical waveguides, Plasma (human), Silicon, Silicon on insulator technology, Waveguides, Line Edge Roughness, Photonic integrated circuits, Propagation loss, Silicon waveguide, smoothing treatments, Roughness measurement |
| ISSN | 10411135 |
| Lien vers article | Link |