Tunnel FET based ultra-low-leakage compact 2T1C SRAM
| Auteurs | Gupta N., Makosiej A., Vladimirescu A., Amara A., Anghel C. |
| Year | 2017-0225 |
| Source-Title | Proceedings - International Symposium on Quality Electronic Design, ISQED |
| Affiliations | MINARC Laboratory, Institut Superieur d'Electronique de Paris (ISEP), France, LETI, Commissariat À l'Energie Atomique et Aux Energies Alternatives (CEA-LETI), France |
| Abstract | In this paper, an ultra-low-leakage 2T1C compact SRAM is proposed using Tunnel FETs (TFETs). Proposed design utilizes negative differential resistance property of TFETs and capacitor leakage to implement 1T1C latch. Additional 1T read port is added for reading to avoid data stability issues during read operation. Proposed SRAM design is scalable and easily adaptable for lower technology nodes. Ultra-low leakage below 1fA/bit is achieved in the proposed design. Read and write cycle times of sub-2ns and sub-4ns are designed. © 2017 IEEE. |
| Author-Keywords | DRAM, eDRAM, Metal-Insulator-Metal (MIM) Capacitors, Tunnel FET |
| Index-Keywords | Dynamic random access storage, Field effect transistors, Logic design, Metal insulator boundaries, MIM devices, Data stabilities, eDRAM, Metal insulator metal capacitor (MIM), Negative differential resistances, Read operation, Technology nodes, Tunnel FET, Ultra low leakages, Integrated circuit design |
| ISSN | 19483287 |
| Lien vers article | Link |