3D interconnect optimization for single channel 100-GBps transmission in a photonic interposer
Auteurs | Morot K., Farcy A., Lacrevaz T., Bermond C., Artillan P., Flechet B., Jacquinot H., Scheiblin P. |
Year | 2017-0278 |
Source-Title | 2017 IEEE 21st Workshop on Signal and Power Integrity, SPI 2017 - Proceedings |
Affiliations | STMicroelectronics, Crolles, France, IMEP-LAHC, Université de Savoie Mont-Blanc, Chambéry, France, CEA-LETI, Grenoble, France |
Abstract | High speed 3D interconnects are a key element in 2.5D interposer technology that is widely investigated for high performance applications. A wide-band electrical modeling and optimization method of the photonic interposer interconnect chains is presented using scalable models developed based on electromagnetic simulations. Resulting models enable fast and accurate assessment of the whole-chain performances for various sets of technology and design parameters. Using these tools, transmission of 100-Gbps signal through Back-end-of-Line (BEOL), Through Silicon Via (TSV) and Redistribution Layer (RDL) chains are improved following two different methods: independent optimization of each interconnect and optimization of the whole chain. Both techniques are compared for TSV-RDL chain case with wide-range parameter variation and for BEOL-TSV-RDL path satisfying design and technology constraints. Optimization results are validated through comparison with 3D-EM simulation, demonstrating the efficiency of proposed methods to optimize the entire 3D-chain. Results would lead to further works including eye-diagram opening and power consumption optimization, geometrical discontinuity modeling and optimized chain integration. © 2017 IEEE. |
Author-Keywords | Chain modeling, Electromagnetic Simulation, Interposer, Optimization, SB-Interconnect, Scattering parameters |
Index-Keywords | Chains, Electromagnets, Integrated circuit interconnects, Optimization, Scattering parameters, Chain models, Electromagnetic simulation, Geometrical discontinuity, High performance applications, Interposer, Power consumption optimizations, Technology and designs, Through-Silicon-Via (TSV), Three dimensional integrated circuits |
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