Dense N over CMOS 6T SRAM cells using 3D Sequential Integration
| Auteurs | Lu C-M.V., Fenouillet-Beranger C., Brocard M., Billoint O., Cibrario G., Brunet L., Garros X., Leroux C., Casse M., Laurent A., Toffoli A., Romano G., Kies R., Gassilloud R., Rambal N., Lapras V., Samson M.-P., Tallaron C., Tabone C., Previtali B., Barge D., Ayres A., Pasini L., Besombes P., Andrieu F., Batude P., Skotnicki T., Vinet M. |
| Year | 2017-0279 |
| Source-Title | 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 |
| Affiliations | STMicroelectronics, Crolles France, France, CEA-Leti MINATEC Campus, Grenoble France, France |
| Abstract | Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 108/mm2 achievable. In addition, we presented N-type devices fabricated below 630°C yielding quasi-equivalent performances as high temperature ones while fulfilling the PBTI and hot-carrier effects reliability requirements, comforting the viability of N over CMOS approach. © 2017 IEEE. |
| Author-Keywords | |
| Index-Keywords | Static random access storage, VLSI circuits, 6t sram cells, 6T-SRAMs, CMOS devices, High temperature, Hot carrier effect, One-pass, Reliability requirements, Top layers, CMOS integrated circuits |
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