Analog parameters on pMOS SOI ?-gate nanowire down to 10 nm width for different back gate bias
| Auteurs | Itocazu V.T., Sonnenberg V., Martino J.A., Barraud S., Vinet M., Faynot O. |
| Year | 2017-0309 |
| Source-Title | Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings |
| Affiliations | LSI, PSI, USP, University of Sao Paulo, Sao Paulo, Brazil, FATEC/SP, FATEC/OSASCO, CEETEPS, Sao Paulo, Brazil, CEA, LETI, Minatec Campus, University Grenoble Alpes, Grenoble, France |
| Abstract | This paper shows for the first time, the influence of back gate bias (VB) in some analog parameters on pMOS Silicon-On-Insulator (SOI) omega-gate nanowire (?G-NW) devices down to 10 nm width (W). An excellent electrostatic control is observed in devices down to 40 nm of channel length. The saturated transconductance slightly increase while the output conductance slightly decrease with VB increment, resulting in an increase of intrinsic voltage gain (AV) up to 30% for wider devices. © 2017 IEEE. |
| Author-Keywords | Back gate, Nanowire, Omega-Gate, p-type, SOI |
| Index-Keywords | Nanowires, Silicon, Silicon on insulator technology, Analog parameters, Back gates, Electrostatic control, Intrinsic voltage gains, Omega gates, Output conductance, P-type, Silicon-on- insulators (SOI), Electrostatic devices |
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