First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts
| Auteurs | Deshpande V., Hahn H., O'Connor E., Baumgartner Y., Sousa M., Caimi D., Boutry H., Widiez J., Brevard L., Le Royer C., Vinet M., Fompeyrine J., Czornomaz L. |
| Year | 2017-0373 |
| Source-Title | Digest of Technical Papers - Symposium on VLSI Technology |
| Affiliations | IBM Research GmbH Zürich Laboratory, Säumerstrasse 4, Rüschlikon, Switzerland, CEA-Leti, MINATEC Campus, Université Grenoble Alpes, 17 rue des Martyrs, Cedex 9, France |
| Abstract | We demonstrate, for the first time, the 3D Monolithic (3DM) integration of In0.53GaAs nFETs on FDSOI Si CMOS featuring short-channel Replacement Metal Gate (RMG) InGaAs n-FinFETs on the top layer and Gate-First Si CMOS on the bottom layer with TiN/W inter-layer contacts. State-of-the-art device integration is achieved with the top layer InGaAs utilizing raised source drain (RSD) and the bottom layer CMOS having Si RSD for nFETs, SiGe RSD for pFETs, implants, silicide and TiN/W plug contacts. The top layer InGaAs n-FinFETs are scaled down to Lg =25 nm and both the Si nFETs and pFETs in the bottom layer are scaled down to Lg ?15 nm. Finally, utilizing the inter-layer contacts, we demonstrate a densely integrated 3D 6T-SRAM circuit with InGaAs nFETs stacked on top of Si pFETs showing considerable area reduction with respect to a 2D layout. © 2017 JSAP. |
| Author-Keywords | |
| Index-Keywords | CMOS integrated circuits, FinFET, Gallium alloys, Indium alloys, Integration, Monolithic integrated circuits, MOSFET devices, Semiconducting indium, Silicides, Silicon, Titanium alloys, Titanium compounds, Titanium nitride, Tungsten alloys, VLSI circuits, Area reduction, Bottom layers, Inter-layers, Metal gate, Monolithic integration, Raised-source drains, Short channels, State-of-the-art devices, Si-Ge alloys |
| ISSN | 7431562 |
| Lien vers article | Link |