In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization
| Auteurs | Miro-Panades I., Beigne E., Billoint O., Thonnart Y. |
| Year | 2017-0449 |
| Source-Title | 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017 |
| Affiliations | Univ. Grenoble Alpes, F-38000 Grenoble, France CEA LETI Minatec Camp., 17 Ave. des Martyrs, 38054, Grenoble Cedex, France |
| Abstract | Achieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circuit is presented which significantly minimizes the operating voltage and tracks it during run-time operation of a circuit without failure. A DSP core embedding this technique has been fabricated and measured. Its Vmin has been estimated within +3.5%/-2.5% at nominal clock frequency (1600MHz), thus reducing by 19% its energy per operation. © 2017 IEEE. |
| Author-Keywords | Design margins reduction, In-situ monitors, TMFLT |
| Index-Keywords | Systems analysis, Clock frequency, Design margin, Efficiency and reliability, Hardware error, In-situ techniques, Operating voltage, Situ monitor, TMFLT, Energy efficiency |
| ISSN | |
| Lien vers article | Link |