Recent advances in low temperature process in view of 3D VLSI integration
| Auteurs | Fenouillet-Beranger C., Batude P., Brunet L., Mazzocchi V., Lu C.-M.V., Deprat F., Micout J., Samson M.-P., Previtali B., Besombes P., Rambal N., Lapras V., Andrieu F., Billoint O., Brocard M., Thuries S., Cibrario G., Acosta-Alba P., Mathieu B., Kerdilès S., Nemouchi F., Arvet C., Besson P., Loup V., Gassilloud R., Garros X., Leroux C., Beugin V., Guerin C., Benoit D., Pasini L., Hartmann J.-M., Vinet M. |
| Year | 2017-0096 |
| Source-Title | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 |
| Affiliations | CEA, Leti, MINATEC Campus, France, STMicroelectronics, France |
| Abstract | In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration. © 2016 IEEE. |
| Author-Keywords | 3D, CoolCube, Laser anneal, low temperature process, monolithic integration |
| Index-Keywords | Budget control, Integration, Microelectronics, Silicides, VLSI circuits, CoolCube, Dopant activation, Gate stacks, Laser anneal, Low- temperature process, Monolithic integration, Stability improvement, Thermal budget, Temperature |
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