Influence of source-drain engineering and temperature on split-capacitance characteristics of FDSOI p-i-n gated diodes
| Auteurs | Sasaki K.R.A., Navarro C., Bawedin M., Andrieu F., Martino J.A., Cristoloveanu S. |
| Year | 2017-0089 |
| Source-Title | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 |
| Affiliations | LSI, PSI, USP, University of Sao Paulo, Sao Paulo, Brazil, IMEP, LAHC, Grenoble, France, CEA, LETI, Grenoble, France |
| Abstract | Motivated by the TFET (tunneling field effect transistor) technology, we investigate the temperature and gate overlap/underlap influence on the capacitance of p-i-n diodes fabricated with UTBB FDSOI. The underlap-overlap architecture modifies the split capacitance curves essentially when the back interface is depleted. As a result, the extracted front gate oxide (tOX) and silicon film thickness (tSi) are accurate, with error below 5%. At high temperature, the capacitance curves are narrower due to the threshold voltage (VT) lowering in n- and p-channels. However, the accuracy of tOX and tSi extraction is only marginally affected. © 2016 IEEE. |
| Author-Keywords | |
| Index-Keywords | Field effect transistors, Microelectronics, Threshold voltage, Capacitance characteristics, Gate overlap, Gate oxide, Gated diodes, High temperature, Silicon film thickness, Source-drain, Tunneling field-effect transistors, Capacitance |
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