​Energy efficiency at the device, chip, board and system levels: ensuring the most efficient use of energy resource

• ICT energy efficiency is one of the greater challenges of our time. According to worst case scenarios, ICTs could represent up to 51% of the world's energy consumption and 23% of greenhouse gases in 2030. Energy consumption of high-performance computer systems, already at 20 MW, is a major technological and economic issue. To compensate the increase in power consumption of mobile devices that accompanies the increase in  their computing capacity, long term research is ongoing to improve battery performance. Short term solutions must thus include drastically lowering the energy budget of intelligent systems used in the Internet of Things (T) to guarantee operation below 1 W. 
  

• This includes lowering standby power consumption, as T devices operate at very low duty cycles. Rethinking the whole family of technologies, from devices to applications, will allow us to meet these challenges and maximize energy efficiency.i is developing technologies and architectures to address ICT power management such as low-power CMOS (FD-SOI, TFET, etc.), neuromorphic circuits based on m memories, computation modules using 3D integration, silicon-based photonics, stacked intelligent 3D imagers, etc. The capacity of both hardware and software to adapt dynamically to environmental conditions and different application requirements is also under study to curtail energy waste.
  

​   Multi-core module based on a 3D interposer and FD-SOI

​   ​Multi-core architecture based on a Silicon Photonics electro-optical interpose

​   Photograph of a 28 FDSOI based DSP VLIW functioning at 460MHz and 400mV

Eye diagram of an optical modulator amplifier functioning at 10Gbps