Cryogenic Integration
- While the advances in basic cryo-CMOS capabilities are exciting, their successful application in practical systems will also require new capabilities in cryogenic packaging. To this end, CEA-Leti is leveraging its state-of-the-art 3D packaging line to develop novel silicon interposers that can be used to assemble quantum dies and their accompanying electronic controllers. The program opens a number of architectural options in terms of die size for qubits and cryo-CMOS, along with the possibility of integrating additional functionalities for transmission between qubits and cores.
The interposer project, which involves a team from CEA-Leti, CEA-List, CEA-IRIG, and the Néel Institute at the French National Centre for Scientific Research (CNRS), illustrates how multiple technological building blocks can be applied to address the many challenges that arise in a project of this scope and complexity.
The interposer’s primary function is to accommodate and connect devices containing both quantum and classical elements, allowing the system to address and read qubits, while also enabling better technological control and easier co-existence of the two types of elements. This requires it to be conveniently compatible with both quantum and control components fabricated by different groups using different processes and materials.
One important advantage of the interposer design is that the qubits and control electronics are coupled by routing lines on the interposer, rather than with a wire-bonding approach. This reduces parasitic capacitance and inductance that complicate measurements. Moreover, through careful choice of materials and processing options, the researchers are working towards the challenging goal of having the interposer provide thermal decoupling of the quantum and control chips, so the quantum elements can be kept at the lowest possible temperature.
Subsequent efforts have focused on related advancements. One is the adaptation of existing CEA-Leti-developed flip-chip processes with die-to-wafer bonding techniques (such as SnAg microbumps and direct Cu-bonded pads with Cu/SiO2 hybrid bonding) to fabricate interconnects that can operate reliably at temperatures below 1K. The CEA-Leti research team won a "best paper" award for their presentation on this achievement at the 2020 Electronics System-integration Technology Conference.
System-Level Low-Temperature Design
- Finally, the overall system design for this type of novel low-temperature system will require careful and clever partitioning of different functions at different temperature stages.
For this reason, the CEA development teams include experienced analog and RF designers working closely with hardware architects and low-level-software engineers to develop a clear pathway to a fully operational integrated system. This will require system-level implementation of different elements (such as digital and analog hardware) at different temperature ranges
These efforts tie closely with the goals of the EU-funded QLSI project, particularly its targets of demonstrating a quantum computer prototype that integrates a high-quality quantum processor in a semi-industrial environment (with up to eight qubits available online), and documentation of the requirements for scalability towards large systems of over 1,000 qubits.
Conclusion
There are, to be sure, many remaining challenges in development of silicon-spin quantum computing. But the rapid and broad-based progress to date, and CEA’s strong foundation of existing knowledge and development capability, are clear indications that its multiinstitute, silicon-oriented approach to quantum computing has much to recommend it. Expertise from an extraordinarily wide range of disciplines is needed, and the long heritage of CEA-Leti and the other CEA institutes in innovating, refining, and applying novel technologies is a perfect match for the demands of this exceptionally complex and challenging development process.