Realization of a QuIC3 demonstrator for 3D co-integration of quantum chips with CryoCMOS FDSOI 28nm control chips is an important step toward a full quantum computing system that operates at a very low temperature, less than 1 K, with optimum control and reading performance, said Maud Vinet, head of CEA-Leti's quantum computing program.

• The interposers’ primary purpose is to accommodate and connect quantum chips containing qubits and control chips, and to address and read the qubits, with two metal levels on the front side of the interposers. Additional on-chip circuits integrated on the interposer provide alternative reading options of information stored in the qubits. To functionalize further the interposer, passive elements and filter devices could be integrated on subsequent versions. The QUI1 (Quantum Interposer n°1) mask set used to build the first interposer was designed during the Covid-19 confinement period by pooling the expertise of CEA-Leti, CEA-List and Néel Institute at CNRS.

This interposer breakthrough is a unique combination of expertise on quantum physics, 3D technologies, material integration, IC interface, passives design and micro-architecture to achieve a solution adapted to quantum computation, Vinet said. The platform optimizes the control and readout of qubits by bringing the control electronics to the vicinity of the quantum chip without wire bonding.

• This proximity of the control electronics and the qubits increases the number of qubits that can be controlled, because it avoids the limitation on the number of lines of the cryostat. Wire bonding is not necessary because the qubits and control electronics are coupled by routing lines on the interposer, which reduces parasitic capacitance and inductance that complicate measurements.
  
• the platform created by the interposer also can allow thermal decoupling of the quantum and control chips to keep the quantum chip at the lowest temperature possible.
  

All of these elements aim to reach very large-scale integration of qubits," Vinet added. Next generations of the interposer will incorporate through silicon vias (TSV) to increase the connection density and eliminate wire bonding.