​The paper reports the first successful technological integration of chiplets on a fully processed, packaged and tested, active silicon interposer. 

Large multi-core 3D systems with multiple chiplets integrated on an active silicon interposer have been proposed to support High Performance Computing (HPC) applications. Using fine-pitch 3D interconnects, chip-to-chip bandwidth has been increased and overall power consumption has been reduced. A chiplet approach allows optimization of industrial yield through smaller dies and reusable IP blocks. While chiplet partitioning is already widespread on passive organic and silicon interposers, its combination with active circuits has not yet been reported. An active interposer allows intelligent features to be added to the final 3D system, such as advanced network-on-chip (NoC) interconnects, fast I/Os for off-chip communication, embedded power management and system-on-chip (SoC) infrastructure. This paper details the first successful integration of chiplets on a fully packaged and tested active silicon interposer with state-of-the-art, 20 µm-pitch, 3D interconnects.

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