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REMINDER

The aim of the REMINDER project is to develop an innovative embedded DRAM solution by removing the capacitor, which normally stores information in a standard DRAM structure. This is called a 1T-DRAM. It uses a device built on SOI substrate to enlarge the FDSOI platform offer. Following development of electrical characterization, simulation, compact modeling and design enablement tools, the ultimate objective is to manufacture a functional memory matrix of some Mbits.


Published on 23 April 2021

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Revolutionary embedded memory for internet of things devices and energy reduction

The aim of the REMINDER project is to develop an innovative embedded DRAM solution by removing the capacitor, which normally stores information in a standard DRAM structure. This is called a 1T-DRAM. It uses a device built on SOI substrate to enlarge the FDSOI platform offer. Following development of electrical characterization, simulation, compact modeling and design enablement tools, the ultimate objective is to manufacture a functional memory matrix of some Mbits.





 

Starting date : Jan. 2017 > Dec. 2020 

Lifetime: 48 months

Program in support : H2020-ICT-25-2015


 

Status project : complete


CEA-Leti's contact :

Joris Lacord

Yves Quéré

 

Project Coordinator: CEA-Leti (FR)


Partners: 

  • German Aerospace Center, (DE)
  • Ibeo Automotive Systems, (DE)
  • IT21, (DE)
  • Objective Software, (DE)
  • Robert Bosch, (DE)
  • Zigpos, (DE)
  • BeSpoon, (FR)
  • CEA-Leti, ( FR)
  • Eurecom, (FR)
  • FBConsulting, (LU)
  • PaulsConsultancy, (NL)
  • Tass International, (NL)
  • Chalmers University of Technology Gothenburg, (SE)



Publications:

 
  • «Z²-FET DC hysteresis: deep understanding and preliminary model», J. Lacord et al., SISPAD 2017.
  • «Optimization guidelines of A2RAM cell performance through TCAD simulations», F. Tcheme-Wakam et al., SISPAD 2017.
  • «Z²-FET SPICE Model: DC and Memory Operation», S. Martinie et al., S3S 2017.
  • «MSDRAM, A2RAM and Z²-FET performance benchmark for 1T-DRAM applications», J. Lacord et al., SISPAD 2018.
  • «Evidence of fast and low-voltage A2RAM ‘1’ state programming», F. Tcheme Wakam, SISPAD 2018.
  • «Doping profile extraction in thin SOI films: Application to A2RAM», F. Tcheme Wakam, EUROSOI 2018.
  • «A comprehensive model on field-effect pnpn devices (Z²-FET)», Y. Taur, SSE 2017.
  • «Ultra-low power 1T-DRAM in FDSOI technology», H. El Dirani et al., microelectronic engineering journal 2017.
  • «Ultra-low power 1T-DRAM in FDSOI technology», M.-S. Parihar et al., ESSDERC 2017.
  • «Impact of carrier lifetime on Z²-FET operation», M.-S. Parihar et al., EUROSOI 2017.
  • «The mystery of the Z²-FET 1T-DRAM memory”, M. Bawedin et al., EUROSOI 2017.
  • «Z²-FET as Capacitor-Less eDRAM Cell For High-Density Integration», C. Navarro et al., ED 2017.
  • «Extended Analysis of the Z²-FET: Operation as Capacitorless eDRAM», C. Navarro et al., TED 2017.
  • «A review of the Z²-FET 1T-DRAM memory: operation mechanisms and key parameters», S. Cristoloveanu, SSE 2017.
  • «Insight into carrier lifetime impact on band-modulation devices», M.-S. Parihar, SSE 2017.
  • «Low-Power Z²-FET Capacitorless 1T-DRAM», M.-S. Parihar, IMW 2017.
  • «Z²-FET memory matrix in 28 nm FDSOI technology», M.-S. Parihar, EUROSOI 2018.

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Investment:  € 4.5 m.

EC Contribution: € 3.6 m.


Website


Stakes

  •  Technology

> An A2RAM cell comprising an SOI transistor with a silicon film (approx. 25nm) thicker than CMOS applications. The film is divided into a top section used used to store information and a bottom section is used to read information. The bottom section is a buried doped layer (a bridge) that short-circuits the source and drain.

> Objective:

• Demonstrate that a nanowire structure can improve A2RAM performance and scaling
• Demonstrate that a heterostructure between the storage region (SiGe material) and the bridge (Si material) can improve A2RAM performance.

> Process flow definition of A2RAM devices using CEA-Leti nanowire exploiting Coolcube technological developments to build the bridge:

• A2RAM structure definition by finite element simulation (TCAD): determining target
film thicknesses, bridge doping and thickness, gate length and Ge quantity in the SiGe storage region
• S/D implanting and annealing steps defined by TCAD
• Bridge implanting and annealing steps defined by TCAD.

> Successful fabrication of nanowire-based A2RAM in a CEA-Leti clean room.

  •  Electrical characterization
> Experimental demonstration of nanowire-based functionality of A2RAM devices:

• Demonstrating bridge presence using capacitive measurements
• Demonstrating memory effect: ‘1’ and ’0’ states can be programmed and read.

  • Simulation
> TCAD environment developed for Z2FET device simulation and shared with REMINDER partners:

• Z2FET device is a partially gated PIN diode on SOI usually dedicated to ESD applications but used here as a 1T-DRAM structure.

> In-depth knowledge of Z2FET device, especially DC hysteresis, through extensive TCAD simulations, forming
the basis of Z2FET compact model development
> TCAD simulation to calibrate the Z2FET compact
model
> TCAD supporting technological development
involving
nanowire-based A2RAM fabrication.

  • Modelling
> Compact model development of Z2FET for
project final demonstrator design: 1T-DRAM matrix using Z2FET devices.
> Z2FET compact model includes:
> DC behavior with hysteresis
> Memory operation (write, erase and read)

  • Other
> Workshop organization for 1T DRAM solutions
at EuroSOI-ULIS 2019 conference in Grenoble.




OBJECTIVES
REMINDER develops an embedded DRAM solution optimized for ultra-low-power consumption and variability immunity, specifically focused on Internet of Things cutting-edge devices. The objectives of REMINDER are:
  •  investigation (concept, design, characterization, simulation, modelling), selection and optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost;
  • design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits, blocks and architectures are carefully analysed from the power-consumption point of view.
In addition, variability tolerant design techniques underpinned by variability analysis and statistical simulation technology are widely considered;
  • demonstration of a system on chip application using the developed memory solution and benchmarking with alternative embedded memory blocks.
The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also require the redesign of different applications, including memory cells, and therefore we also propose the evaluation of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative materials.
The fulfilment of the objectives above also implies the development of:
  • new techniques for the electrical characterization of ultimate CMOS nanometric devices. This allows us to improve the CMOS technology by boosting device performance;
  • new behavioural models, incorporating variability effects, to reach a deep understanding of nanoelectronics devices;
  • advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices;
  • extreme low power solutions.
The consortium supporting this project is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.


IMPACT

  • When functional, the 1T DRAM matrix demonstrator will be a first demonstration of a 1T DRAM matrix on SOI. Close cooperation has been set up between partners Granada University, Glasgow University and Grenoble’s
    IMEP-LAHC laboratory, especially for TCAD simulation and electrical characterization.