Starting date : Mar. 2019 > Feb. 2025 Lifetime: 72 months
Program in support :
Status of project : in progress
CEA-Leti's contact:
Project Coordinator: CEA-IRIG (FR), Institut Néel CNRS (FR), CEA-Leti (FR)
Partners: - DE: German Aerospace Center Ibeo Automotive Systems, IT21, Objective Software, Robert Bosch, Zigpos
- FR: BeSpoon, CEA-Leti, Eurecom
- LU: FBConsulting
- NL: PaulsConsultancy, Tass International
- SE: Chalmers Universityof Technology Gothenburg
Investment: € 14 mi
EC Contribution: € 14 mi
Releases«A CMOS silicon spin qubit», R. Maurand, X. Jehl, D. Kotekar-Patil, A. Corna, H. Bohuslavskyi, R. Laviéville, L. Hutin, S. Barraud, M. Vinet, M. Sanquer, and others, Nat. Commun. 7, 13575 (2016).
«Efficient controlled-phase gate for single-spin qubits in quantum dots», T. Meunier, V. Calado, and L. Vandersypen,Phys. Rev. B 83, 121403(R) (2011).
«Opportunities brought by sequential 3D CoolCube™ integration», M. Vinet, P. Batude, C. Fenouillet-Beranger, L. Brunet, V. Mazzochi, C.-M.V. Lu, F. Deprat, J. Micout, B. Previtali, P. Besombes, and others, in Solid-State Device Res. Conf. (ESSDERC), 2016 46th Eur. (2016), pp. 226–229.
| Stakes
- On a technical level, the QuCube project is original and a cornerstone in several ways. CEA-Leti is providing its unique know-how in 3D integration processes, including smart-cut and waferbonding methods [Fou00], semiconductor epitaxy[Wid14], ground-breaking Cool-CubeTM and high density technologies [Vin16, Viv17] for vertical integration of functional devices (e.g.transistors and memories) with unprecedented alignment accuracy (<5nm).
- The QuCube project will use 300-mm SOI wafers with an isotopically purified 28Si device layer, currently being grown at CEA-Leti. In addition, CEA-Leti’s and CEA-Inac’s extensive skills in device modeling andsi mulation [Niq16] (Y.-M. Niquet’s teams) are ensuring highly valuable guidance in designing and optimizing qubit devices.
- CEA-Leti and its partners have demonstrated 99% fidelity in spin read-out [urd19] in 2019. Our teams have ensure the migration of the qubit technology to immersion lithography with a 20 nm critical dimension and a 80nm pitch, and have fabricated 28Si qubit test structures for low temperature characterization. A Trans Impedance Amplifier (TIA) has been designed [leg19] to increase throughput under these conditions. This relies on low a compact low temperature FDSOI model calibrated using an accurate low temperature technology characterization [paz19].
OBJECTIVES
- Originally conceived to describe the microscopic world of atoms and elementary particles, theoretical quantum mechanics was eventually used to predict macroscopic phenomena, e.g. semiconductor electrical and optical properties, resulting a wide range of technological applications that have changed our lifestyle. However, foundational properties such as quantum superposition and entanglement have remained essentially unexploited. Their use may allow us to achieve computation powers that are inaccessible to conventional digital computers, thereby offering unprecedented opportunities.
- In a quantum computer, the elementary data bits are encoded on two-level quantum systems called qubits. Since qubits interact with the uncontrolled degrees of freedom of their environment, changes in their quantum states can quickly become unpredictable, leading to reduced qubit fidelity. In topological quantum computing schemes, e.g. the surface code, lower fidelity is compensated by using decoherence-free logical qubits composed of a many (~103) entangled physical qubits. An effective quantum processor should therefore accommodate millions of qubits, at least. Although dauntingly large, this number is still small compared to the number of transistors in modern silicon microprocessors.
- QuCube is leveraging industrial-level silicon technology to build a quantum processor containing hundreds of spin qubits confined to a two-dimensional array of electrostatically defined silicon quantum dots. To overcome the challenge of addressing the qubits individually, we hnave adopted a 3-dimensional architecture designed to accommodate, on separate planes, the charge sensing devices required for qubit readout and the metal gate lines for electrical control and measurement. The gate lines are operated on a multiplexing basis to provide a scalable wiring layout. Fault-tolerant logical qubits and quantum simulations of complex Hamiltonians will be implemented.
IMPACT
- Through its fabrication and operation of quantum processors integrating at least a hundred qubits, the aim of the QuCube project is to break ground towards large scale qubit integration. When available, the targeted quantum processors will provide a sizable test bench for testing and optimizing system-specific quantum correction algorithms and for evaluating the best upscaling strategy.
In principle, the proposed qubit architecture is designed to be scalable up to millions of qubits, but alternative scaling routes may be investigated based on the outcome of this project (e.g. architectures based on fairly small qubit arrays operating as logical qubits, well separated from each other and connected by long range quantum buses; these have not been produced but may soon become available).
We are not aware of any alternative qubit platform offering large scale qubit integration (millions of qubits would seem necessary for a useful fault-tolerant quantum processor). In this sense, the QuCube project has a clearly high-risk/high-gain profile. The know-how and IP generated by QuCube could contribute to the development of a European spinoff company ensuring industrialization and subsequent commercialization.
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