You are here : Home > Projet NEURAM3

Europe | Tools ＆ research instruments


NEURAM3

The NEURAM 3 project partners have fabricated a mixed-signal analog/digital chip based on neuromorphic architecture that supports state-of-the-art machine learning and spike-based learning mechanisms. In architecture terms, this chip features an ultra-low power, scalable and highly configurable neural architecture that can deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions. 


Published on 23 April 2021

​

NEURAM3: NEUral computing aRchitectures In Advanced Monolithic 3D-VLSI nano-technologies

The NEURAM 3 project partners have fabricated a mixed-signal analog/digital chip based on neuromorphic architecture that supports state-of-the-art machine learning and spike-based learning mechanisms. In architecture terms, this chip features an ultra-low power, scalable and highly configurable neural architecture that can deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions. The project also made progress towards developing monolithically integrated 3D technology in Fully-Depleted Silicon on Insulator (FDSOI) based on 28nm design rules with integrated Resistive Random Access Memory (RRAM) synaptic elements.


 
 


 

Starting date: Jan. 2016 > Jun. 2019  Lifetime:42 months

Program in support : ERC Consolidator grant

 

Status project: complete

CEA-Leti's contact: Elisa Vianello                                    

 

Project Coordinator: CEA-Leti 


Partners:  

  • Imec (BE)
  • IBM Zurich, UZH Switzerland (CH)
  • IMSE (ES)
  • JACU (GER)
  • ST Microelectronics (FR)
  • CNR (FR)
  • Stichting IMEC (NL)


​Target market: n/a

​

Publications 

1] D. R. B. Ly et al., IEEE IEDM 2019 Tech. Dig., 10.1109/
IEDM.2018.8614603. CEA-Leti.
[2] T. Dalgaty et al., APL Materials 7, 081125 (2019); https://
doi.org/10.1063/1.5108663. CEA-Leti/UZH.
[3] A. Valentian et al., IEEE IEDM 2019 Tech. Dig., 10.1109/
IEDM19573.2019.8993431. CEA-Leti.

  • «An event-based classifier for Dynamic  An event-based classifier for Dynamic Vision Sensor and synthetic data», E. Stromatias, M. Soto, M.T. Serrano Gotarredona, B. Linares Barranco, Frontiers in Neuroscience, 11 (2017).

  • «Mapping of local and global synapses on spiking neuromorphic hardware», A. Das, Y. Wu, K. Huynh,F. Dell’Anna, F. Catthoor, S. Schaafsma, 2018 Design,Automation & Test in Europe Conference & Exhibition (DATE).

  • «A differential memristive synapse circuit for on-line learning in neuromorphic computing systems», M.V. Nair, L.K. Muller, G. Indiveri, Nano Futures 1.3 (2017): 035003.

  • «An Ultralow Leakage Synaptic Scaling Homeostatic Plasticity Circuit With Configurable Time Scales up to 100 ks», N. Qiao, C. Bartolozzi, G. Indiveri, IEEE Transactions on Biomedical Circuits and Systems, PP:(99), 2017.

  • «Stimulated Ionic Telegraph Noise in FilamentaryMemristive Devices», S. Brivio, J. Frascaroli, E. Covi, S. Spiga, Scientific Report 9, 6310 (2019). DOI: 10.1038/s41598- 019-41497-3 (Gold Open Access).


​

Investment:  € 4.1 m.

EC Contribution: € 3.2 m.


Website


Stakes

  • CEA-Leti has presented the first complete integration of a SNN combining analog neurons and RRAM-based synapses. The implemented topology was a perceptron designed to perform hand-written digit classification (MNIST database). Measured classification accuracy was 84% with a 3.6 pJ energy dissipation per spike at synapse and neuron level (up to 5x lower than similar chips using formal coding).


  • First demonstration of integration of a full 3D CMOS over CMOS CoolCubeTM with two 1T1R. One 1R was connected to the top transistor and the other to the bottom MOSFET. The top level was integrated with state-of-the-art high-performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate and raised source and drain.

  • CEA-Leti has designed and fabricated of a resistive memory-based Content Addressable Memory (CAM) [2]. The proposed CAM cell was largely insensitive to the resistive memory resistance ratio and variability. This circuit allows routing implementation (i.e. sending spikes
    among neurons) in reconfigurable neuromorphic hardware. This solution offers a smaller area requirement (2 transistors and 2 resistive memories) than conventional solutions (12 transistors) and it is non-volatile (no static power consumption).



OBJECTIVES

  • NeuRAM3 has developed complementary technologies that address the full spectrum of applications from mobile/autonomous objects to high performance computing co-processing, by developing, (1) a technology to implement on-chip learning using
    native adaptive characteristics of electronic synaptic elements and, (2) a scalable platform to interconnect multiple neuromorphic processor chips for building large neural processing systems.


  • The neuromorphic computing system has been developed in conjunction with advanced neural algorithms and computational architectures for online adaptation, learning and high-throughput on-line signal processing. This delivers:
    > An ultra-low power, massively parallel, non-Von Neumann, computing platform with non-volatile nano-scale devices that
    support on-line learning mechanisms
    > A programming toolbox of algorithms and data structures tailored to the physical architecture’s specific constraints and
    opportunities
    > An array of fundamental application demonstrations materializing the basic classes of signal processing tasks. The neural chip validates the concept and represents an important first step towards developing a European technology platform spanning ultra-low power data processing in autonomous systems (Internet of Things) to energy-efficient large data processingin servers and networks.



IMPACT

  • A new EU ICT RIA project (#871371) to advance the NeuRAM3 outcomes has been approved and was started in January 2020. This focuses onmemory technologies with multi-scale time constants for neuromorphic architectures (MeM-Scales).