VASCO 2
An ASIC to highlight the latest innovations in component security
VASCO 2 (ASIC vehicle for component security) integrates innovative, patented hardware security building blocks on 22 nm FD-SOI silicon. It enables all types of standard or customized tests to validate these technologies in operational conditions in order to prepare a transfer to industry.
VASCO 2 highlights the relevance and characteristics of these hardware block for industry by matching current challenges in hardware security:
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Securing processors
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Securing and accelerating pre- and post-quantum cryptography
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Modelization and characterization of True Random Number Generators (TRNG)
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Securing memories, etc.
What's new?
For the first time, VASCO 2 integrates hardware security block on 22 nm FD-SOI silicon:
- 32-bits RISC-V core processor secured against physical attacks
- C-SRAM (Computational SRAM) for near memory matrix computing
- Security functions around SRAM (PUF, fast erase)
- TRNG modelization and validation block • Hybrid accelerator to optimize and secure the computation of pre-quantum signature algorithms and post-quantum encryption
Performance (power consumption, cycle time, surface) and security (analysis of side-channels, laser fault injection EM fault injection) have been characterized in real conditions.
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What's next?
With VASCO 2, manufacturers have access to comprehensive data on hardware security block: security level, power consumption, silicon surface area, and impact on cycle time.
CEA can help industrial partners characterize security features and adapt this block to meet their specifications in terms of application constraints and their transition to FD-SOI. This design phase lasts approximately 12 months.
CEA is constantly monitoring evolutions in security requirements, and accordingly, continues to develop new hardware block. At the end of 2024, this block will be integrated and characterized (security and performance) on a new "VASCO 3" ASIC that includes a 64-bit RISC-V processor
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