University Grenoble Alpes, CEA-LETI, Minatec Campus, Grenoble, France

Monolithic 3D Integration technology (M3D) provides high density vertical interconnects allowing new design approaches such as Cell-on-Cell (gate level approach) and NMOS-on-PMOS (transistor level approach). This work proposes a 3D Cell-on-Buffer (3DCoB) design approach by separating the logical functioning stage of a gate from its driving stage, then vertically stacking them. The proposed 3DCoB approach demonstrates better performances compared to the 2D implementation and the conventional 3D approaches. A Multi-VDD low-power technique is applied to 3DCoB cells (i.e. a different power supply for each tier). The multi-VDD 3DCoB technique provides total power reduction with limited performances degradation compared to the single-VDD 3DCoB approach. 3DCoB with single- and Multi- VDD techniques are applied on a set of benchmark designs in 28 nm-FDSOI technology using conventional sign-off place and route flow. Implementation results show up to 35% increment in performance and up to 21.8% reduction in the total power compared to 2D designs. © 2016 Elsevier Ltd

3DVLSI, Cell-on-Buffer, CoolCube, High-density 3D integrated circuits, Monolithic 3D

Benchmarking, Cells, Cytology, Integrated circuit design, Low power electronics, Three dimensional integrated circuits, Timing circuits, 3-D integration, 3DVLSI, Benchmark designs, CoolCube, Design approaches, Low power techniques, Place and route, Transistor level, Monolithic integrated circuits