CEA-LETI, MINATEC, Grenoble, Cedex 9, France, MAPPER Lithography, Delft, Netherlands

Massively parallel electron beam direct write (MP-EBDW) lithography is a cost-effective patterning solution, complementary to optical lithography, for a variety of applications ranging from 200 to 14 nm. This paper will present last process/integration results to achieve targets for both 28 and 45nm nodes. For 28nm node, we mainly focus on line-width roughness (LWR) mitigation by playing with stack, new resist platform and bias design strategy. The lines roughness was reduced by using thicker spin-on-carbon (SOC) hardmask (%14%) or non-chemically amplified (non-CAR) resist with bias writing strategy implementation (%20%). Etch transfer into trilayer has been demonstrated by preserving pattern fidelity and profiles for both CAR and non-CAR resists. For 45nm node, we demonstrate the electron-beam process integration within optical CMOS flows. Resists based on KrF platform show a full compatibility with multiple stacks to fit with conventional optical flow used for critical layers. Electron-beam resist performances have been optimized to fit the specifications in terms of resolution, energy latitude, LWR and stack compatibility. The patterning process overview showing the latest achievements is mature enough to enable starting the multi-beam technology pre-production mode. © 2017 The Japan Society of Applied Physics.

Carbon, Cost effectiveness, Electron beam lithography, Electron beams, Electrons, Lithography, Photolithography, System-on-chip, Chemically amplified, Electron beam direct write, Electron beam resist, Linewidth roughness, Massively parallel electron beams, Process Improvement, Process integration, Strategy implementations, Roughness measurement