Low-power Z2-FET capacitorless 1T-DRAM
| Description | |
| Date | |
| Authors | Parihar M.S., Lee K.H., Dirani H.E., Navarro C., Lacord J., Martinie S., Barbe J.-Ch., Fonteneau P., Galy Ph., Le Royer C., Mescot X., Gamiz F., Cheng B., Asenov A., Taur Y., Bawedin M., Cristoloveanu S. |
| Year | 2017-0271 |
| Source-Title | 2017 IEEE 9th International Memory Workshop, IMW 2017 |
| Affiliations | IMEP-LAHC, CNRS, Univ. Grenoble Alpes, France, STMicroelectronics, 850 rue Jean Monnet, Crolles-Cedex, France, Univ. of Granada, Spain, CEA-LETI, Minatec Campus, Grenoble, France, Synopsys, Glasgow, United Kingdom, Univ. of Glasgow, United Kingdom, Univ. of California, San Diego, United States |
| Abstract | This work highlights the features of Z2-FET capacitorless 1T-DRAM describing its operation in detail. The Z2-FET memory cell fabricated with FDSOI technology delivers large current sense margin along with long retention time at room temperature. Numerous measurements confirm that the demonstrated 1T-DRAM is able to achieve attractive current margin even with 0.5 V programming voltage. For this case, the power consumption is also reduced by restricting the writing current. Abovementioned merits along with significantly small OFF-state current makes this device a suitable candidate for low power embedded DRAM applications. © 2017 IEEE. |
| Author-Keywords | 1T-DRAM, Current margin, FDSOI, Low-power, SOI, Z2-FET |
| Index-Keywords | 1t drams, Current margins, FDSOI, Low Power, Z<sup>2</sup>-FET, Dynamic random access storage |
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| Link | Link |