High density emerging resistive memories: What are the limits?
| Description | |
| Date | |
| Authors | Levisse A., Giraud B., Noel J.P., Moreau M., Portal J.M. |
| Year | 2017-0280 |
| Source-Title | LASCAS 2017 - 8th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference: Proceedings |
| Affiliations | Univ. Grenoble Alpes, Grenoble, France, CEA, LETI, MINATEC Campus, Grenoble, France, Aix-MarseiUe Université, IM2NP, CNRS UMR 7334, Marseille, France |
| Abstract | With the saturation of the Flash memory technologies scaling under the 20nm nodes, new technology opportunities are explored by both industrial and academic research teams. Resistive switching memories are today seen as the most promising replacement candidate for both embedded (NOR) and stand-alone (NAND) flash memories. The native Back-End-of-Line (BEoL) integration enabled by the RRAM technologies opens the way for new 3D architectures such as crosspoint or Vertical-RRAM, and triggers the development of novel BEoL selection devices. These architectures bring new design challenges, for instance, sneaking currents through unselected bitcells (SneakPaths), voltage drop along deeply scaled (<50nm) metal lines (IRdrop) and peripheral circuitry overhead. In this paper, we introduce two physical IRdrop models for crosspoint and Vertical-RRAM architectures. We also introduce a peripheral circuitry model for crosspoint architecture. Using these models, we show that both periphery overhead and IRdrop limit the crosspoint architecture under 50nm of half pitch. © 2017 IEEE. |
| Author-Keywords | High Density, NVM, OxRAM, Resistive Switching Memories, Scaling |
| Index-Keywords | Flash memory, Industrial research, Memory architecture, RRAM, Switching systems, Back end of lines, Design challenges, OxRAM, Peripheral circuitry, Resistive switching memory, Scaling, Selection devices, Technology opportunities, Random access storage |
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| Link | Link |