High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process
| Description | |
| Date | |
| Authors | Morillon D., Julien F., Coignus J., Toffoli A., Welter L., Jahan C., Reynard J.-P., Richard E., Masson P. |
| Year | 2017-0290 |
| Source-Title | IEEE International Conference on Microelectronic Test Structures |
| Affiliations | STMicroelectronics, France, CEA LETI, Minatec Campus, Grenoble, France, EpOC / Nice Sophia-Antipolis University, Biot, France |
| Abstract | This paper presents the performance and reliability evaluation of high voltage MOS gate stacks integrated in an advanced CMOS technology platform. The aim of this study is to evaluate the compatibility of a thick silicon dioxide with a high-k metal gate stack which replaces the standard polysilicon gate. Using capacitors, physical, electrical, and reliability characterizations are carried out and TiN metal gate is found to be a potential issue as it induces a high density of interfacial traps. Despite these traps, oxide lifetime could still meet demanding requirements. Thus, using the high-k metal gate stack on top of a thick SiO2 gate oxide could be a potential solution for high voltage transistors integration on advanced CMOS platforms with embedded non-volatile memories. © 2017 IEEE. |
| Author-Keywords | |
| Index-Keywords | CMOS integrated circuits, Gates (transistor), Logic gates, Metals, Microelectronics, MOS devices, Silica, Silicon oxides, High voltage transistor, HIGH-K metal gates, Interfacial traps, Non-volatile memory, Performance and reliabilities, Polysilicon gates, Reliability characterization, Thick gate oxides, MOSFET devices |
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| Link | Link |