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Performance and transport analysis of vertically stacked p-FET SOI nanowires

Published on 29 March 2018
Performance and transport analysis of vertically stacked p-FET SOI nanowires
Description
 
Date 
Authors
Paz B.C., Pavanello M.A., Cassé M., Barraud S., Reimbold G., Vinet M., Faynot O.
Year2017-0312
Source-TitleJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
Affiliations
Department of Electrical Engineering, Centro Universitário da FEI, São Bernardo do Campo, Brazil, Département des Composants Silicium, SCME, LCTE, CEA, LETI, Minatec, Grenoble, France
Abstract
This work presents the performance and transport characteristics of vertically stacked p-MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. Electrical characterization is performed for NWs with [110] and [100] channel orientations, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15nm gate length. Improved effective mobility is obtained for [110]-oriented NWs due to higher sidewall mobility contribution. © 2017 IEEE.
Author-Keywords
channel orientation, electrical characterization, performance, SOI MOSFET, transport, vertically stacked nanowire
Index-Keywords
MOSFET devices, Si-Ge alloys, Silicon alloys, Channel orientations, Electrical characterization, performance, SOI-MOSFETs, transport, Nanowires
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