Improved analog performance of SOI Nanowire nMOSFETs Self-Cascode through back-biasing
| Description | |
| Date | |
| Authors | Assalti R., De Souza M., Cassé M., Barraud S., Reimbold G., Vinet M., Faynot O. |
| Year | 2017-0314 |
| Source-Title | Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings |
| Affiliations | Department of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil, Département des Composants Silicium, SCME, LCTE, CEA, LETI, Minatec, Grenoble, France |
| Abstract | In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated. © 2017 IEEE. |
| Author-Keywords | analog performance, asymmetric self-cascode, back gate voltage, channel width, silicon nanowire |
| Index-Keywords | Cascode amplifiers, Electric breakdown, MOSFET devices, Nanowires, Silicon, Threshold voltage, Analog performance, Back-gate voltages, Channel widths, Self-cascode, Silicon nanowires, Analog circuits |
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| Link | Link |