Institute of Materials Microelectronics and Nanosciences of Provence - UMR CNRS 7334, Aix-Marseille University, Marseille, France, Institut des Nanotechnologies deLyon, CNRSUMR 5270, Villeurbanne, France, CMP, University Grenoble Alpes, Grenoble, France, University Grenoble Alpes, Grenoble, France, CEA, LETI, MINATEC Campus, Grenoble, France

Emerging nonvolatile memories (NVM) based on resistive switching mechanism such as RRAM are under intense R&amp,D investigation by both academics and industries. They provide high write/read speed, low power, and good endurance (e.g., &gt,1012) beyond mainstream NVMs, enabling them to be a good candidate for Flash replacement in microcontroller unit. This replacement could significantly decrease the power consumption and the integration cost on advanced CMOS nodes. This paper presents first the HfO2-based RRAM technology and the associated compact model, which includes related physics and model card fitting experimental electrical characterizations. The 128 kb memory architecture based on RRAM technology and 28 nm fully depleted silicon on insulator (FDSOI) CMOS core process is presented with a bottom-up approach, starting from the bit-cell definition up to the complete memory architecture implementation. The key points of the architecture are the use of standard logic MOS exclusively, avoiding any high voltage MOS usage, program/verify procedure to mitigate cycle to cycle variability issue and direct bit-cell read access for characterization purpose. The proposed architecture is validated using postlayout simulations on MOS and RRAM corner cases. © 2002-2012 IEEE.

Embedded non-volatile memory, memory architecture, resistive switching memory, RRAM

CMOS integrated circuits, Data storage equipment, Digital storage, Hafnium oxides, Integrated circuit design, Memory architecture, Nonvolatile storage, Random access storage, RRAM, Switching systems, Electrical characterization, Emerging non-volatile memory, Fully depleted silicon-on-insulator, Non-volatile memory, Post layout simulation, Proposed architectures, Resistive switching mechanisms, Resistive switching memory, Silicon on insulator technology