FDSOI vs FinFET: Differentiating device features for ultra low power & IoT applications
| Description | |
| Date | |
| Authors | |
| Year | 2017-0360 |
| Source-Title | 2017 IEEE International Conference on IC Design and Technology, ICICDT 2017 |
| Affiliations | CEA-Leti, MINATEC Campus, 17 rue des Martyrs, Grenoble, Cedex 9, France, STMicroelectronics, 850 rue Jean Monnet, Crolles, France |
| Abstract | This paper reviews the main differentiating features of planar FDSOI devices vs planar bulk and 3D FinFETs for ultra-low power and IoT (Internet of Things) applications. The interest of using back-bias, the specific FDSOI device/design feature, to maximize the performance/power efficiency, to mitigate the process variability and to suppress the leakage is highlighted in this paper. Low parasitic gate capacitance, low VT mismatch associated with its undoped channel, and low gate resistance linked to the gate-first integration also bring some competitive advantages to FDSOI over FinFETs for Analog and RF devices. © 2017 IEEE. |
| Author-Keywords | FinFETs, Fully Depleted silicon-on-insulator (FDSOI) |
| Index-Keywords | Competition, FinFET, MOSFET devices, Silicon on insulator technology, Competitive advantage, FinFETs, Fully depleted silicon-on-insulator, Gate capacitance, Gate resistance, IOT applications, Process Variability, Undoped channels, Internet of things |
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| Link | Link |