New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling
| Description | |
| Date | |
| Authors | Garros X., Laurent A., Barraud S., Lacord J., Faynot O., Ghibaudo G., Reimbold G. |
| Year | 2017-0374 |
| Source-Title | Digest of Technical Papers - Symposium on VLSI Technology |
| Affiliations | CEA-LETI, 17 rue des Martyrs, Grenoble, France, IMEP-LAHC, Minatec, INPG, Grenoble, France |
| Abstract | In this paper we deeply investigate the dependence of BTI with transistor scaling. Unlike PBTI, NBTI is strongly enhanced in narrow devices like Nanowire or Finfet. We clearly prove by means of 3D electrostatic simulations that it is due to a defect density at the Sidewall (SW) of the transistor about 2.5 times higher than the one at the Top Surface (TS). © 2017 JSAP. |
| Author-Keywords | |
| Index-Keywords | Defect density, Surface defects, 3D technology, Electrostatic simulations, Top surface, Transistor scaling, VLSI circuits |
| ISSN | 7431562 |
| Link | Link |