Key process steps for high performance and reliable 3D Sequential Integration
| Description | |
| Date | |
| Authors | Lu C.-M.V., Deprat F., Fenouillet-Beranger C., Batude P., Garros X., Tsiara A., Leroux C., Gassilloud R., Nouguier D., Ney D., Federspiel X., Besombes P., Toffoli A., Romano G., Rambal N., Delaye V., Barge D., Samson M.-P., Previtali B., Tabone C., Pasini L., Brunet L., Andrieu F., Micoud J., Skotnicki T., Vinet M. |
| Year | 2017-0376 |
| Source-Title | Digest of Technical Papers - Symposium on VLSI Technology |
| Affiliations | CEA-LETI, MINATEC Campus, Université Grenoble Alpes, 17 rue des Martyrs, Grenoble, France, STMicroelectronics, Crolles, France |
| Abstract | This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration. © 2017 JSAP. |
| Author-Keywords | 3D sequential integration, gate stack reliability, iBEOL ULK reliability, low thermal budget process flow |
| Index-Keywords | Budget control, Logic gates, Tin oxides, Tungsten, VLSI circuits, Gate stacks, Native oxide removal, Performance and reliabilities, Process flows, Process integration, Solid phase epitaxy, State of the art, Technological modules, Reliability |
| ISSN | 7431562 |
| Link | Link |