STMicroelectronics, Crolles, France, University of Grenoble Alpes, Grenoble, France, CEA-LETI, MINATEC Campus, Grenoble, France

In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted-silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the postlayout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node. © 2017 IEEE.

3-D monolithic, back bias, fully depleted-silicon on insulator (FD-SOI), read assist, static random access memory (SRAM)

Integrated circuit design, Random access storage, Semiconducting silicon, Static random access storage, Critical operations, Data dependent, Failure mechanism, Fully depleted silicon-on-insulator, Parasitic element, Static random access memory, Technology nodes, Technology platforms, Silicon on insulator technology