IMS Laboratory, University of Bordeaux, Talence, France, CEA, LETI, MINATEC, Grenoble, France

This paper presents the design of an Ultra Low Power (ULP) inductorless Low Noise Amplifier (LNA) based on a Common Gate (CG) architecture using the back gate control of the Fully-Depleted Silicon-On-Insulator (FDSOI) technology. It demonstrates the potential of the back biasing to lower the power consumption of more than 30 % compared to a design without back biasing, while keeping similar performance. This paper also shows the possibility with the back gate control of this technology to reach additional performance, suitable for the design of tunable LNAs. The proposed LNA has been implemented in ST-Microelectronic 28 nm FDSOI Technology and its active area is only 0.0015 mm2. The measured performance exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF) and an Input referred third-order Intercept Point (IIP3) of-16 dBm. The total power consumption is 300 ?W from a 0.6 V supply. The same LNA reached other performance modes at constant Figure of Merit (FoM). © 2017 IEEE.

Body bias, Fully Depleted Silicon-On-Insulator (FDSOI), Inductorless, Low Noise Amplifier (LNA), Tunability, Ultra Low Power (ULP)

Amplifiers (electronic), Electric power utilization, Low noise amplifiers, Low power electronics, Microelectronics, Noise figure, Power inductors, Variable frequency oscillators, Body bias, Fully depleted silicon-on-insulator, Inductorless, Tunabilities, Ultra low power, Silicon on insulator technology