STMicroelectronics, Noida, India, IIIT Delhi, New Delhi, India, STMicroelectronics, Crolles, France, CEA-LETI, MINATEC, Grenoble, France

An optimized co-design of SRAM cell, assist schemes, and layout is proposed to achieve wide voltage range operation of SRAM from 0.35-1.2 V at all process corners. A differential read asymmetric 8 T memory cell and a data dependent differential supply and body modulation write assist scheme are proposed. We also propose a layout that reduces metal capacitance of wordlines by 54% and also enables bit-interleaving. The proposed assist scheme can be combined with conventional assist schemes to further lower minimum write operational voltage of the SRAM by 70-130 mV at iso-performance without causing reliability concerns. A 32 kb instance is fabricated in 28-nm UTBB-FDSOI technology and efficiency of the proposed scheme is demonstrated with lowest write voltage of 0.32 V. Multiple read assist schemes have been used to simultaneously lower read voltage to 0.35 V. 50 MHz operation is measured when integrated in a DSP processor at 0.358 V. Low voltage and wide voltage range figure of merits are also defined to benchmark the proposed solutions with other works. © 2004-2012 IEEE.

bit-interleaved SRAM, FDSOI, Low voltage SRAM, multiple wordline, voltage scaling, wide voltage range SRAM, write assist

Capacitance, Cells, CMOS integrated circuits, Cytology, Dynamic random access storage, Integrated circuit layout, Logic gates, Voltage scaling, Circuit stability, FDSOI, Layout, Low voltages, Low-voltage SRAM, SRAM Cell, Voltage ranges, Wordlines, write assist, Static random access storage