Adiabatic capacitive logic: A paradigm for low-power logic
| Description | |
| Date | |
| Authors | Pillonnet G., Fanet H., Houri S. |
| Year | 2017-0453 |
| Source-Title | Proceedings - IEEE International Symposium on Circuits and Systems |
| Affiliations | Univ. Grenoble-Alpes, CEA-LETI, Grenoble, France, Tech. Univ. Delft, Delft, Netherlands |
| Abstract | Although CMOS technology scaling combined with efficient frequency and voltage scaling strategies offer femto Joule per logic operation, energy consumption remains orders of magnitude above the limit given by information theory. To alleviate this inherent energy dissipation, this paper introduces a new paradigm: the adiabatic capacitive logic. Based on adiabatic operation, the principle also relies on a smooth capacitance modulation to achieve a quasi zero-power logic dissipation. This method limits leakage by using metal-metal junctions instead of semiconductor one. It also avoids dynamic power consumption by adiabatic transitions. The contact-less operation promises a better reliability compared to logic based on nano-mechanical relays. © 2017 IEEE. |
| Author-Keywords | adiabatic logic, low-power, mems, variable capacitor |
| Index-Keywords | Capacitance, Energy dissipation, Energy utilization, Information theory, MEMS, Semiconductor junctions, Voltage scaling, Adiabatic logic, Adiabatic operations, Adiabatic transitions, Capacitance modulation, Dynamic power consumption, Low Power, Variable capacitor, Voltage scaling strategies, Computer circuits |
| ISSN | 2714310 |
| Link | Link |