Ultra-thin dielectric insertions for contact resistivity lowering in advanced CMOS: Promises and challenges
| Description | |
| Date | |
| Authors | Borrel J., Hutin L., Kava D., Gassilloud R., Bernier N., Morand Y., Nemouchi F., Gregoire M., Dubois E., Vinet M. |
| Year | 2017-0197 |
| Source-Title | Japanese Journal of Applied Physics |
| Affiliations | CEA, LETI, Minatec Campus, Grenoble, France, STMicroelectronics, 850 Rue Jean Monnet, Crolles, France, IEMN, UMR 8520 CNRS, Avenue Poincaré, Villeneuve D'Ascq Cedex, France, Department of Electrical and Computer Engineering, University of Texas at El Paso, El Paso, TX, United States |
| Abstract | In this paper, in order to provide a comprehensive overview of the opportunities and limitations of the metal/insulator/semiconductor contacts approach, expected performance based on ideal contact simulations as well as key practical aspects are presented. While the former give us a glimpse of the theoretical potential of this paradigm, mainly to contact nFETs, the latter highlights concerns about the electrical characterization of such contacts along with issues occurring during their physical implementation. © 2017 The Japan Society of Applied Physics. |
| Author-Keywords | |
| Index-Keywords | Physical properties, Physics, Advanced CMOS, Contact resistivities, Contact simulation, Dielectric insertion, Electrical characterization, Performance based, Ultra-thin, CMOS integrated circuits |
| ISSN | 214922 |
| Link | Link |