Univ. Grenoble Alpes, Grenoble, France, CEA, LETI, MINATEC Campus, Grenoble, France

We have examined 200 mm GaN on silicon wafers, while varying the AlN nucleation temperature, and have found that higher temperatures result in a more convex bow on the wafers. In addition, by performing full wafer defect mapping, we have found that a higher nucleation temperature results in a higher density of inverted pyramid defects, which have previously been found to reduce the breakdown voltage of GaN on silicon layers. We have performed electrical measurements on a wafer with the lowest temperature AlN layer, which is still within our bow specification, and which therefore has the lowest density of inverted pyramid defects. This wafer showed the same leakage current density for both very small and very large test structures (2×10?3 and 18.7 mm2 respectively), with all but one of our large structures maintaining a breakdown voltage greater than 700 V. This is a very promising result for high yield of devices on 200 mm GaN on silicon wafers. © 2016 Elsevier B.V.

A1. Defects, A1. Nucleation, A3. Metal-organic vapor phase epitaxy, B1. Nitrides

Defect density, Defects, Electric breakdown, Gallium nitride, Metallorganic vapor phase epitaxy, Nucleation, Organometallics, Silicon, AlN layers, Defect mapping, Electrical measurement, GaN on silicon, Large structures, Metal-organic vapor phase epitaxy, Nucleation temperature, Test structure, Silicon wafers