Univ. Grenoble Alpes, Grenoble, France, CEA, LETI, MINATEC Campus, Grenoble, France, CNRS, TIMA Laboratory, Université Grenoble Alpes, Grenoble, France

With the emergence of manycore processors with potentially hundreds of processors in the embedded market, the scalability of cache coherence protocols is again at stake. One seemingly simple issue is the management of the set of sharers of a memory block, but with that many processors, it is a major bottleneck in terms of hardware resources. In this paper, we define a high level simulation method to evaluate sharing set management strategies, using memory access traces obtained through cycle accurate simulation (e.g. gem5). The goal of the method is to rank protocols based on latency, traffic and hardware cost, to help either choose an existing approach for a given application context, or evaluate new approaches. We demonstrate the applicability of our proposal by evaluating three existing scalable cache coherence protocols, obtaining results consistent with previous, low level, evaluations much more rapidly. © Springer International Publishing AG 2017.

Cache memory, Computer architecture, Hardware, Memory architecture, Application contexts, Cache coherence protocols, Cycle-accurate simulation, Hardware resources, High level simulation, Management strategies, Many-core processors, New approaches, Multiprocessing systems