CEA-LETI, Minatec Campus, 17 rue des Martyrs, Grenoble, France, STMicroelectronics, 850 rue Monnet B.P. 16, Crolles, France, CEMES-CNRS, 29 Rue Jeanne Marvig, Toulouse Cedex 4, France

A novel dual isolation scheme with both Shallow Trench Isolation (STI) and local oxidation, so called Dual Isolation by Trenches and Oxidation (DITO), is presented to maximize the stress induced by SiGe channel and the back-biasing efficiency at the same time in FDSOI technology. DITO integration experimentally demonstrates +36% pMOSFET drive current at same leakage, which is translated into -23% ring-oscillator delay reduction at a supply voltage of Vdd=0.8V. It is found that this gain is attributed to 0.45GPa saved compressive stress in the longitudinal direction, compared to the standard STI isolation. On top of that, DITO enables the Vt tuning in an extended range for both nMOS and pMOS independently through back-bias application in both reverse and forward modes. +29% and 1 decade leakage extensions are provided by this full range Vt tuning compared to the standard single STI and well FDSOI architecture where only one back-bias mode is allowed. DITO thus leverages highly-stressed and highly-tunable devices for both high performance and low power applications. © 2016 IEEE.

Compressive stress, Efficiency, Electron devices, Tuning, Delay reduction, Local oxidation, Longitudinal direction, Low power application, Maximum Efficiency, Ring oscillator, Shallow trench isolation, Supply voltages, Semiconducting silicon