Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain
| Description | |
| Date | |
| Authors | Barraud S., Lapras V., Samson M.P., Gaben L., Grenouillet L., Maffini-Alvaro V., Morand Y., Daranlot J., Rambal N., Previtalli B., Reboh S., Tabone C., Coquand R., Augendre E., Rozeau O., Hartmann J.M., Vizioz C., Arvet C., Pimenta-Barros P., Posseme N., Loup V., Comboroure C., Euvrard C., Balan V., Tinti I., Audoit G., Bernier N., Cooper D., Saghi Z., Allain F., Toffoli A., Faynot O., Vinet M. |
| Year | 2017-0130 |
| Source-Title | Technical Digest - International Electron Devices Meeting, IEDM |
| Affiliations | CEA, LETI, MINATEC Campus and Univ., Grenoble Alpes, Grenoble, France, STMicroelectronics, 850 rue J. Monnet, Crolles, France |
| Abstract | "We report on vertically stacked horizontal Si NanoWires (NW) /""-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs. © 2016 IEEE." |
| Author-Keywords | |
| Index-Keywords | Electron devices, Nanowires, Silicon alloys, Compressive strain, Different stages, Fabrication process, Precession electron diffractions, Short channels, SiGe source/drain, Source-drain, Strain fields, MOSFET devices |
| ISSN | 1631918 |
| Link | Link |