Design of optimized high Q inductors on SOI substrates for RF ICs
| Description | |
| Date | |
| Authors | Royet A.S., Michel J.P., Reig B., Pornin J.L., Ranaivoniarivo M., Robain B., De Person P., Uren G. |
| Year | 2017-0152 |
| Source-Title | 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 |
| Affiliations | CEA, LETI, DCOS Division, MINATEC Campus, Grenoble, France, ALTIS Semiconductor, Corbeil Essonnes, France |
| Abstract | This paper presents several experimental and simulation results on 130 nm SOI integrated inductors. Measurements and 3D electromagnetic simulations highlight the efficiency of different layout techniques and technological choices to improve the integrated inductor Q factor. We compare a variable-width spiral inductor with a classical spiral inductor keeping the inductance value constant as an essential parameter for RF circuit designers. A 30% Q factor enhancement is achieved for a same size device and same inductance value. The paper will attempt to provide keys to compromise between Q factor optimization and inductor compactness. The influence of the ratio between internal and external width of the coil's turns and the wire space is also examined. © 2016 IEEE. |
| Author-Keywords | quality factor, RF SOI integrated spiral inductors, series resistance losses, variable width inductor design |
| Index-Keywords | Electric resistance, Inductance, Integrated circuit design, Integrated circuits, Q factor measurement, Timing circuits, Electromagnetic simulation, High-Q inductors, Inductance values, Inductor design, Integrated inductors, Integrated spiral inductors, Quality factors, Series resistances, Electric inductors |
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| Link | Link |