Cost model for monolithic 3D integrated circuits
| Description | |
| Date | |
| Authors | Gitlin D., Vinet M., Clermidy F. |
| Year | 2017-0095 |
| Source-Title | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 |
| Affiliations | CEA, Leti, Palo Alto, CA, United States, CEA, Leti, MINATEC Campus, 17 rue des martyrs, Grenoble, France |
| Abstract | A cost model for monolithic 3D-ICs is presented that takes into account increased process complexity and associated yield impact as well as area reduction. The model enables more accurate PPC (Power, Performance and Cost) understanding and the range of applicability for monolithic 3D-IC technology. The model shows that depending on the die area and partitioning scheme, the cost benefit can be 50% or higher. © 2016 IEEE. |
| Author-Keywords | 3D IC, CoolCube™, Cost, PPC, Yield |
| Index-Keywords | Cost benefit analysis, Costs, Microelectronics, Monolithic integrated circuits, Timing circuits, 3-D ICs, Area reduction, Cost benefits, Cost modeling, Die area, IC technology, Process complexity, Yield, Three dimensional integrated circuits |
| ISSN | |
| Link | Link |