Back gate bias influence on SOI ?-gate nanowire down to 10 nm width
| Description | |
| Date | |
| Authors | Almeida L.M., Agopian P.G.D., Martino J.A., Barraud S., Vinet M., Faynot O. |
| Year | 2017-0087 |
| Source-Title | 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 |
| Affiliations | LSI, PSI, USP, University of Sao Paulo, Sao Paulo, Brazil, UNESP - Univ. Estadual Paulista, Sao Joao da Boa Vista, Brazil, CEA, LETI, Minatec Campus, University Grenoble Alpes, Grenoble, France |
| Abstract | We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure. © 2016 IEEE. |
| Author-Keywords | Back gate, Nanowire, Omega-Gate, SOI |
| Index-Keywords | Digital devices, Microelectronics, Silicon on insulator technology, Analog parameters, Back gates, Gate-all-around, Intrinsic voltage gains, Nanowire devices, Omega gates, Silicon-on- insulators (SOI), Sub-threshold swing(ss), Nanowires |
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| Link | Link |