Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K
| Description | |
| Date | |
| Authors | Paz B.C., Cassé M., Barraud S., Reimbold G., Vinet M., Faynot O., Pavanello M.A. |
| Year | 2017-0141 |
| Source-Title | Solid-State Electronics |
| Affiliations | Department of Electrical Engineering, Centro Universitário da FEI, São Bernardo do Campo, Brazil, Département des Composants Silicium – SCME/LCTE, CEA-LETI Minatec, Grenoble, France |
| Abstract | This work presents an analysis of the performance of silicon triple gate SOI nanowires aiming the investigation of analog parameters for both long and short channel n-type and p-MOSFETs. Several nanowires with fin width as narrow as 9.5 nm up to quasi-planar MOSFETs 10 ?m-wide are analyzed. The fin width influence on the analog parameters is studied for n-type and p-MOSFETs with channel lengths of 10 ?m and 40 nm, at room temperature. The temperature influence is analyzed on the analog performance down to 100 K for long channel n-MOSFETs by comparing the quasi-planar device to the nanowire with fin width of 14.5 nm. The intrinsic voltage gain, transconductance and output conductance are the most important figures of merit in this work. An explicit correlation between these figures of merit and the mobility behavior with temperature is demonstrated. © 2016 Elsevier Ltd |
| Author-Keywords | Analog performance, Fin width influence, Mobility, Nanowires, Temperature influence |
| Index-Keywords | Carrier mobility, Fins (heat exchange), Nanowires, Analog parameters, Analog performance, Figures of merits, Fin widths, Intrinsic voltage gains, Mobility behavior, Output conductance, Temperature influence, MOSFET devices |
| ISSN | 381101 |
| Link | Link |