Reliable gate stack and substrate parameter extraction based on C-V measurements for 14 nm node FDSOI technology
| Description | |
| Date | |
| Authors | Mohamad B., Leroux C., Rideau D., Haond M., Reimbold G., Ghibaudo G. |
| Year | 2017-0137 |
| Source-Title | Solid-State Electronics |
| Affiliations | CEA-Leti, MINATEC Campus, Grenoble, France, Univ. Grenoble Alpes, IMEP-LAHC, MINATEC/INPG, CS 50257, Grenoble, France, STMicroelectronics, BP 16, France |
| Abstract | Effective work function and equivalent oxide thickness are fundamental parameters for technology optimization. In this work, a comprehensive study is done on a large set of FDSOI devices. The extraction of the gate stack parameters is carried out by fitting experimental CV characteristics to quantum simulation, based on self-consistent solution of one dimensional Poisson and Schrodinger equations. A reliable methodology for gate stack parameters is proposed and validated. This study identifies the process modules that impact directly the effective work function from those that only affect the device threshold voltage, due to the device architecture. Moreover, the relative impacts of various process modules on channel thickness and gate oxide thickness are evidenced. © 2016 Elsevier Ltd |
| Author-Keywords | Buried oxide thickness, Channel thickness, Effective work function, Equivalent oxide thickness, Fully depleted silicon on insulator |
| Index-Keywords | Extraction, Logic gates, Parameter extraction, Quantum chemistry, Schrodinger equation, Substrates, Threshold voltage, Work function, Buried oxide thickness, Channel thickness, Effective work function, Equivalent oxide thickness, Fully depleted silicon-on-insulator, Silicon on insulator technology |
| ISSN | 381101 |
| Link | Link |