Further scaling of Si-based devices below 10nm gate length is becoming challenging due to the control of thin channel thickness. For gate length smaller than 10nm, sub-5nm thick Si channel is required. However, the process-induced Si consumption and the reduction of carrier mobility in ultrathin Si layer can limit the channel thickness scaling. Today, the main contenders that allow the extension of the roadmap to ultra-scaled devices are 2D materials, particularly the semiconducting transition metal dichalcogenides (TMD). Due to their unique atomically layered structure, they offer improved immunity to short-channel-effects in comparison to usual Si-based field-effect-transistors (FETs). This makes them very attractive for the application of more-Moore electronics. However, the scalability of MOSFET device and the introduction of new material make source and drain contact a major issue. If many efforts have been made, in the past years, to reduce Fermi level pinning and Schottky barrier height, for many, these approaches are not industrially scalable. The main objective of this work is then to propose an in-depth understanding of electrical contact characteristics (based on different material) to identify the lowest contact resistance. The processes involved, offering an optimal contact resistance, must be compatible with wafer-scale processing for an integration in our 200/300mm advanced CMOS platform. The post-doc will in-depth study mechanisms enabling the formation of small contact resistances (between MoS2 and metal). It will have to identify the most promising contact material and to develop the associated deposition processes (ALD/PVD). Finally, electrical characterization of contact will be performed to qualify both material and interfaces enabling optimal operation of future 2D FETs