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PsD-DRT-22-0075

Published on 7 December 2023
PsD-DRT-22-0075
Research FieldElectronics and microelectronics - Optoelectronics

Domaine-S

ThemeEngineering sciences

Theme-S

Domaine
Electronics and microelectronics - Optoelectronics Engineering sciences DRT DCOS SCCS LCEF Grenoble
Title
Effect of TSV presence on BEOL reliability for 3-layer stacked CMOS image sensor (CIS)
Abstract
Because conventional downsizing based on the empirical Moore's law has reached its limitations, an alternative integration technology, such as three-dimensional integration (3DI) is becoming the mainstream. The 3rd generation of CMOS image sensor (CIS) stacks up to 3 die interconnected by hybrid bonding and High Density Through Silicon Vias (HD-TSVs). Devices and circuits good functioning and integrity have to be maintained in such an integration especially in the close neighborhood of TSVs. Thermal budget, copper pumping, thin wafer warpage can lead to electrical yield and reliability concerns and must be investigated. The work consists in evaluating the impact of TSV processing and proximity on BEOL and FEOL performance and reliability. Acquired data sets will help to define design rules and in particular a potential Keep-Out Zone (KOZ) and calibrate a finite element model (FFM).
Location
Département Composants Silicium (LETI) Service Caractérisation, Conception et Simulation Laboratoire Caractérisation Electrique et Fiabilité
Pcontact
MOREAU Stéphane CEA DRT/DCOS//LCFC CEA-Leti MINATEC Campus, 17 rue des Martyrs 38054 GRENOBLE Cedex 9 + 33 (0)4-38-78-06-36
Start date 
Contact personstephane-nico.moreau@cea.fr

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