PsD-DRT-10-5629
| Research Field | Ultra-divided matter, Physical sciences for materials
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| Domaine-S | Materials and applications
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| Theme | Condensed matter physics, chemistry & nanosciences
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| Theme-S | Engineering sciences
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| Domaine | Ultra-divided matter, Physical sciences for materials
Condensed matter physics, chemistry & nanosciences
Materials and applications
Engineering sciences
DRT
DPFT
SDEP
LDJ
Grenoble
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| Title | Silicon nanowire elaboration for microelectronic applications
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| Abstract | In order to realize high capacity integrated capacitor, one approach consists in developing electrode with high specific surface. In this work, we propose to perform capacitor integrating silicon nanowires. The first part of this study will be devoted to the understanding and to the optimization of Si nanowires CVD growth process. In parallel, properties of nanowires obtained by electrochemical silicon etching will be assessed and will be compared to CVD nanowires characteristics. According to the electrical performances, different strategies (metallization Silicuration…) will be envisaged in order to enhance their electrical conductivity.
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| Location | Département des Plateformes Technologiques (LETI)
Service des procédés de Dépôts
Laboratoire
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| Pcontact | JOUSSEAUME
Vincent
CEA
DRT/DPFT/SDEP/LDJ
17, Avenue des Martyrs
38054 Grenoble cedex 9
0438789522
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| Start date | 1/9/2010 |
| Contact person | vincent.jousseaume@cea.fr
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